View IDT70V3319S133PRFI_2509819.PDF datasheet online --- IC-ON-LINE

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?2003 integrated device technology, inc. may 2003 dsc 5623/7 1 functional block diagram features: true dual-port memory cells which allow simultaneous access of the same memory location high-speed data access ? commercial: 3.6ns (166mhz)/4.2ns (133mhz) (max.) ? industrial: 4.2ns (133mhz) (max.) selectable pipelined or flow-through output mode ? due to limited pin count pl/ ft option is not supported on the 128-pin tqfp package. device is pipelined outputs only on each port. counter enable and repeat features dual chip enables allow for depth expansion without additional logic full synchronous operation on both ports ? 6ns cycle time, 166mhz operation (6gbps bandwidth) ? fast 3.6ns clock to data out ? 1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166mhz ? data input, address, byte enable and control registers ? self-timed write allows fast cycle time separate byte controls for multiplexed bus and bus matching compatibility dual cycle deselect (dcd) for pipelined output mode lvttl- compatible, single 3.3v (150mv) power supply for core lvttl compatible, selectable 3.3v (150mv) or 2.5v (100mv) power supply for i/os and control signals on each port industrial temperature range (-40c to +85c) is available at 133mhz. available in a 128-pin thin quad flatpack, 208-pin fine pitch ball grid array, and 256-pin ball grid array supports jtag features compliant to ieee 1149.1 ? due to limited pin count, jtag is not supported on the 128-pin tqfp package. high-speed 3.3v 256/128k x 18 synchronous dual-port static ram with 3.3v or 2.5v interface idt70v3319/99s dout 0-8_l b w 0 l b w 1 l din_l oe l ub l lb l r/ w l ce 0l ce 1l ab ft /pipe l 0/1 1b 0b 1a 0a 1 0 1/0 0b 1b 0a 1a ab ft /pipe l 1/0 repeat r a 17r (1) a 0r cn ten r ads r dout0-8_r dout9-17_r i/o 0r -i/o 17r din_r addr_r oe r ub r lb r r/ w r ce 0r ce 1r ft /pipe r clk r , counter/ address reg. b w 1 r b w 0 r ft /pipe r counter/ address reg. cnten l ads l re peat l dout9-17_l i/o 0l -i/o 17l a 17 l (1) a 0l addr_l 5623 tbl 01 256k x 18 memory array clk l , jtag tck trst tms tdo tdi ba 0/1 0b 1b 0a 1a 1 0 1/0 1b 0b 1a 0a a b 1/0 note: 1. a 17 is a nc for idt70v3399.
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 2 description: the idt70v3319/99 is a high-speed 256/128k x 18 bit synchronous dual-port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. with an input data register, the idt70v3319/99 has been optimized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. the 70v3319/99 can support an operating voltage of either 3.3v or 2.5v on one or both ports, controllable by the opt pins. the power supply for the core of the device (v dd ) remains at 3.3v. pin configuration (1,2,3,4,5) notes: 1. a 17 is a nc for idt70v3399. 2. all v dd pins must be connected to 3.3v power supply. 3. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 4. all v ss pins must be connected to ground supply. 5. package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 6. this package code is used to reference the package diagram. 7. this text does not indicate orientation of the actual part-marking. 17 16 15 14 12 13 10 9 8 7 6 5 4 3 2 1 11 a b c d e f g h j k l m n p r t u i/o 9l nc v ss tdo a 2l a 4l clk l a 8l a 12l a 16l nc opt l nc v ss nc tdi a 1l a 5l a 9l a 13l a 17l (1 ) v ddql i/o 9r v ddqr pipe/ ft l a 3l a 6l nc a 10l a 14l nc nc nc v ss i/o 10l nc nc i/o 11l nc v ddqr i/o 10r nc i/o 11r nc v ss v dd nc i/o 12 l v dd v ss v ss nc v ss i/o 12r repeat r nc i/o 14l v ddqr v ddql i/o 15r nc v ss nc nc a 15l a 11l a 7l a 0l nc i/o 7l nc i/o 6l i/o 8r ub l nc i/o 8l v ddql ce 0l ce 1l lb l repeat l oe l i/o 0l i/o 2l i/o 1r ads r r/ w r nc i/o 16r i/o 15l trst a 13r a 12r nc v dd clk r i/o 0r nc nc nc nc a 17r (1) tck tms a 5r a 9r ce 0r ce 1r v dd v ss nc nc nc a 16r nc nc a 14r a 10r ub r v ss v ddql i/o 1l i/o 2r nc nc nc a 15r a 11r a 7r lb r oe r v ss nc v ddql opt r nc 70v3319/99bf bf-208 (6) 208-pin fpbga top view (7) 5623 drw 02c i/o 14r v ddql v ss v ddqr nc nc nc nc i/o 7r nc r/ w l nc ads l v ddql i/o 13r cnten l v ss i/o 13l v ss i/o 16l v ddqr v ss i/o 17 r i/o 17l v ddql v ss pipe/ ft r a 8r cnten r a 6r a 3r a 1r a 2r a 0r i/o 3l i/o 4l a 4r v dd v ss v ss v ss v ddqr v ddql v ss v ddqr v ss i/o 3r i/o 4r v ss v ddqr v ss v dd v ss v dd v ss i/o 5r i/o 5l v ddqr i/o 6r v ss v ss v ddql v dd v ss v ddqr v ss v ss v dd v dd v ss v dd v ss 08/01/02
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 3 pin configuration (1,2,3,4,5) (con't.) notes: 1. a 17 is a nc for idt70v3399. 2. all v dd pins must be connected to 3.3v power supply. 3. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 4. all v ss pins must be connected to ground supply. 5. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 6. this package code is used to reference the package diagram. 7. this text does not indicate orientation of the actual part-marking. 70v3319/99bc bc-256 (6) 256-pin bga top view (7) e16 i/o 7r d16 i/o 8r c16 i/o 8l b16 nc a16 nc a15 nc b15 nc c15 nc d15 nc e15 i/o 7l e14 nc d14 nc d13 v dd c12 a 6l c14 opt l b14 v dd a14 a 0l a12 a 5l b12 a 4l c11 ads l d12 v ddqr d11 v ddqr c10 clk l b11 repeat l a11 cnten l d8 v ddqr c8 nc a9 ce 1l d9 v ddql c9 lb l b9 ce 0l d10 v ddql c7 a 7l b8 ub l a8 nc b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 a 14l b5 a 15l c5 a 13l d5 v ddql a4 b4 nc c4 a 16l d4 pipe/ ft l a3 nc b3 tdo c3 v ss d3 nc d2 i/o 9r c2 i/o 9l b2 nc a2 tdi a1 nc b1 nc c1 nc d1 nc e1 i/o 10r e2 i/o 10l e3 nc e4 v ddql f1 i/o 11l f2 nc f4 v ddql g1 nc g2 nc g3 i/o 12l g4 v ddqr h1 nc h2 i/o 12r h3 nc h4 v ddqr j1 i/o 13l j2 i/o 14r j3 i/o 13r j4 v ddql k1 nc k2 nc k3 i/o 14l k4 v ddql l1 i/o 15l l2 nc l3 i/o 15r l4 v ddqr m1 i/o 16r m2 i/o 16l m3 nc m4 v ddqr n1 nc n2 i/o 17r n3 nc n4 pipe/ ft r p1 nc p2 i/o 17l p3 tms p4 a 16r r1 nc r2 nc r3 trst r4 nc t1 nc t2 tck t3 nc t4 a 17r (1) p5 a 13r r5 a 15r p12 a 6r p8 nc p9 lb r r8 ub r t8 nc p10 clk r t11 cnten r p11 ads r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 a 14r t14 a 0r r14 opt r p14 nc p15 nc r15 nc t15 nc t16 nc r16 nc p16 i/o 0l n16 nc n15 i/o 0r n14 nc m16 nc m15 i/o 1l m14 i/o 1r l16 i/o 2r l15 nc l14 i/o 2l k16 i/o 3l k15 nc k14 nc j16 i/o 4l j15 i/o 3r j14 i/o 4r h16 i/o 5r h15 nc h14 nc g16 nc g15 nc g14 i/o 5l f16 i/o 6l f14 i/o 6r f15 nc r9 ce 0r r11 repeat r t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r , e5 v dd e6 v dd e7 v ss e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 v ss f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h6 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 v ss j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 v ss j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 v ss l7 v ss l8 v ss m5 v dd m6 v dd m7 v ss m8 v ss n5 v ddqr n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 v ss f11 v ss 5623 drw 02d , f3 i/o 11r 08/01/02 a 17l (1)
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 4 pin configuration (1,2,3,4,5,8,9) (con't.) notes: 1. a 17 is a nc for idt70v3399. 2. all v dd pins must be connected to 3.3v power supply. 3. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 4. all v ss pins must be connected to ground supply. 5. package body is approximately 14mm x 20mm x 1.4mm. 6. this package code is used to reference the package diagram. 7. this text does not indicate orientation of the actual part-marking. 8. pipe/ ft option in pk-128 is not supported due to limitation in pin count. device is pipelined outputs only on each port. 9. due to the limited pin count, jtag is not supported in the pk-128 package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 70 69 68 67 66 65 91 71 a 14l a 15l a 16l a 17l (1) io 9l io 9r v ddql v ss io 10l io 10r v ddqr v ss io 11l io 11r io 12l io 12r v dd v dd v ss v ss io 13r io 13l io 14r io 14l io 15r io 15l v ddql v ss io 16r io 16l v ddqr v ss io 17r io 17l a 17r (1) a 16r a 15r a 14r a 1r a 0r opt r io 0l io 0r v ddqr v ss io 1l io 1r v ddql v ss io 2l io 2r io 3l io 3r io 4l io 4r v ss v ss v dd v dd io 5l io 5r v ddqr v ss io 7r io 7l v ddql v ss v ss io 8r io 8l v ss opt l a 0l a 1l io 6r io 6l 70v3319/99prf pk-128 (6) 128-pin tqfp top view (7) 5623 drw 02a a 1 3 l a 1 2 l a 1 1 l a 1 0 l a 9 l a 8 l a 7 l u b l l b l c e 1 l c e 0 l v d d v d d v s s v s s c l k l o e l r / w l a d s l c n t e n l r e p e a t l a 6 l a 5 l a 4 l a 3 l a 2 l a 1 3 r a 1 2 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r u b r l b r c e 1 r c e 0 r v d d v d d v s s v s s c l k r o e r r / w r a d s r c n t e n r r e p e a t r a 6 r a 5 r a 4 r a 3 r a 2 r 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 . 08/06/02
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 5 pin names left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables (6 ) r/ w l r/ w r read/write enab le oe l oe r output enable a 0l - a 17l (1 ) a 0r - a 17r (1 ) address i/o 0l - i/o 17l i/o 0r - i/o 17r data input/output clk l clk r clock pipe/ ft l (5) pipe/ ft r (5 ) pipeline/flow-through ad s l ads r address strobe enable cnten l cnten r counter enable repeat l repeat r counter repeat (4 ) ub l ub r upper byte enable (i/o 9 -i/o 17 ) (6 ) lb l lb r lower byte enable (i/o 0 -i/o 8 ) (6 ) v ddq l v ddqr power (i/o bus) (3.3v or 2.5v) (2 ) opt l opt r option for selecting v ddqx (2,3) v dd power (3.3v) (2) v ss ground (0v) tdi test data input tdo test data output tck test logic clock (10mhz) tms test mode select trst reset (initialize tap controller) 5623 tbl 01 1. a 17 is a nc for idt70v3399. 2. v dd , opt x , and v ddqx must be set to appropriate operating levels prior to applying inputs on the i/os and controls for that port. 3. opt x selects the operating voltage levels for the i/os and controls on that port. if opt x is set to vih (3.3v), then that port's i/os and controls will operate at 3.3v levels and v ddqx must be supplied at 3.3v. if opt x is set to vil (0v), then that port's i/os and address controls will operate at 2.5v levels and v ddqx must be supplied at 2.5v. the opt pins are independent of one another?both ports can operate at 3.3v levels, both can operate at 2.5v levels, or either can operate at 3.3v with the other at 2.5v. 4. when repeat x is asserted, the counter will reset to the last valid address loaded via ads x . 5. pipe/ ft option in pk-128 package is not supported due to limitation in pin count. device is pipelined output mode only on each port. 6. chip enables and byte enables are double buffered when pl/ ft = v ih , i.e., the signals take two cycles to deselect. notes:
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 6 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , repeat = v ih . 3. oe is an asynchronous input signal. truth table i?read/write and enable control (1,2,3) oe clk ce 0 ce 1 ub lb r/ w upper byte i/o 9-17 lower byte i/o 0-8 mode x hxxxx high-z high-zdeselected?power down x x l x x x high-z high-z deselected?power down x l h h h x high-z high-z both bytes deselected x lhhll high-z d in write to lower byte only x lhlhl d in high-z write to upper byte only x lhlll d in d in write to both bytes l lhhlh high-z d out read lower byte only l lhlhh d out high-z read upper byte only l lhllh d out d out read both bytes h l h l l x high-z high-z outputs disabled 5623 tb l 0 2 truth table ii?address counter control (1,2) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. read and write operations are controlled by the appropriate setting of r/ w , ce 0 , ce 1 , ub , lb and oe . 3. outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle. 4. ads and repeat are independent of all other memory control signals including ce 0 , ce 1 and ub , lb . 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other memory control signals including ce 0 , ce 1 , ub , lb . 6. when repeat is asserted, the counter will reset to the last valid address loaded via ads . this value is not set at power-up: a known location should be loaded via ads during initialization if desired. any subsequent ads access during operations will update the repeat address location. external address previous internal address internal address used clk ads cnten repeat (6 ) i/o (3) mode xxan xx l (4 ) d i/o (0) counter reset to last valid ads load an x an l (4) xhd i/o (n) external address used an ap ap hh h d i/o (p) external address blocked?counter disabled (ap reused) xapap + 1 h l (5) hd i/o (p+1) counter enabled?internal address generation 5623 tb l 0 3
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 7 recommended operating temperature and supply voltage (1) recommended dc operating conditions with v ddq at 2.5v absolute maximum ratings (1) notes: 1. undershoot of v il > -1.5v for pulse width less than 10ns is allowed. 2. v term must not exceed v ddq + 100mv. 3. to select operation at 2.5v levels on the i/os and controls of a given port, the opt pin for that port must be set to v il (0v), and v ddqx for that port must be supplied as indicated above. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 150mv for more than 25% of the cycle time or 4ns maximum, and is limited to < 20ma for the period of v term > v dd + 150mv. 3. ambient temperature under bias. no ac conditions. chip deselected. notes: 1. this is the parameter ta. this is the "instant on" case temperature. grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v3.3v + 150mv industrial -40 o c to +85 o c0v3.3v + 150mv 5623 tbl 04 symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supp ly voltage (3 ) 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high voltage (address & control inputs) 1.7 ____ v ddq + 100mv (2 ) v v ih input high voltage - i/o (3) 1.7 ____ v ddq + 100mv (2 ) v v il input low voltage -0.3 (1) ____ 0.7 v 5623 tbl 05a symbol rating commercial & industrial unit v term (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v t bias (3) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out dc output current 50 ma 5623 tbl 06 recommended dc operating conditions with v ddq at 3.3v notes: 1. undershoot of v il > -1.5v for pulse width less than 10ns is allowed. 2. v term must not exceed v ddq + 150mv. 3. to select operation at 3.3v levels on the i/os and controls of a given port, the opt pin for that port must be set to v ih (3.3v), and v ddqx for that port must be supplied as indicated above. symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih inp ut hig h vo ltage (address & control inputs) (3) 2.0 ____ v ddq + 150mv (2) v v ih inp ut hig h vo ltage - i/o (3) 2.0 ____ v ddq + 150mv (2) v v il input low voltage -0.3 (1) ____ 0.8 v 5623 tbl 05b
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 8 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 150mv) note: 1. at v dd < 2.0v leakages are undefined. 2. v ddq is selectable (3.3v/2.5v) via opt pins. refer to p.5 for details. symbol parameter test conditions 70v3319/99s unit min. max. |i li | input leakage current (1 ) v ddq = max., v in = 0v to v ddq ___ 10 a |i lo | output leakage currentt (1 ) ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (2) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (2 ) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (2) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (2 ) i oh = -2ma, v ddq = min. 2.0 ___ v 5623 tbl 08 notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . capacitance (1) (t a = +25c, f = 1.0mh z ) symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 8 pf c out (3) output capacitance v out = 3dv 10.5 pf 5623 tbl 07
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 9 dc electrical characteristics over the operating temperature and supply voltage range (3) (v dd = 3.3v 150mv) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 120ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v cc - 0.2v ce x > v cc - 0.2v means ce 0x > v cc - 0.2v or ce 1x - 0.2v "x" represents "l" for left port or "r" for right port. 70v3319/99s166 com'l only 70v3319/99s133 com'l & ind symbol parameter test condition version typ. (4 ) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1) com'l s 370 500 320 400 ma ind s ____ ____ 320 480 i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih , outputs disabled, f = f max (1) com'l s 125 200 115 160 ma ind s ____ ____ 115 195 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5 ) active port outputs disabled, f=f max (1) com'l s 250 350 220 290 ma ind s ____ ____ 220 350 i sb3 full standby current (both ports - cmos level inputs) both ports outputs disabled ce l and ce r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v, f = 0 (2 ) com'l s 15 30 15 30 ma ind s ____ ____ 15 40 i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (5) v in > v dd - 0.2v or v in < 0.2v active port, outputs disabled, f = f max (1 ) com'l s 250 350 220 290 ma ind s ____ ____ 220 350 5623 tbl 09
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 10 ac test conditions (v ddq - 3.3v/2.5v) figure 1. ac output test load. figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig. figure 3. typical output derating (lumped capacitive load). input pulse levels (address & controls) input pulse lev els (i/os) input ris e/fall times input timing re fe renc e lev els output reference levels output load gnd to 3 . 0v/gnd to 2.4v gnd to 3.0v/gnd to 2.4v 2ns 1.5v/1.25v 1.5v/1.25v figures 1 and 2 5623 tbl 10 1.5v/1.25 50 ? 50 ? 5623 drw 03 10pf (tester) data out , 5623 drw 04 590 ? 5pf* 435 ? 3.3v data out , 833 ? 5pf* 770 ? 2.5v data out , -1 1 2 3 4 5 6 7 20.5 30 50 80 100 200 10.5pf is the i/o capacitance of this device, and 10pf is the ac test load capacitance. capacitance (pf) ? tcd (typical, ns) 5623 drw 05 ? ? ? ? ,
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 11 ac electrical characteristics over the operating temperature range (read and write cycle timing) (2,3) (v dd = 3.3v 150mv, t a = 0c to +70c) notes: 1. the pipelined output parameters (t cyc2 , t cd2 ) apply to either or both left and right ports when ft /pipe x = v ih . flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v il for that port. 2. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ) and ft /pipe. ft /pipe should be treated as a dc signal, i.e. steady state during operation. 3. these values are valid for either level of v ddq (3.3v/2.5v). see page 5 for details on selecting the desired operating voltage levels for each port. 70v3319/99s166 com'l only 70v3319/99s133 com'l & ind symbol parameter min. max. min. max. unit t cyc1 clock cycle time (flow-through) (1) 20 ____ 25 ____ ns t cyc2 clock cycle time (pipelined) (1) 6 ____ 7.5 ____ ns t ch1 clock high time (flow-through) (1) 6 ____ 7 ____ ns t cl1 clock lo w time (flo w-thro ug h) (1) 6 ____ 7 ____ ns t ch2 clock high time (pipelined) (2) 2.1 ____ 2.6 ____ ns t cl2 clock low time (pipelined) (1) 2.1 ____ 2.6 ____ ns t sa address setup time 1.7 ____ 1.8 ____ ns t ha address hold time 0.5 ____ 0.5 ____ ns t sc chip enable setup time 1.7 ____ 1.8 ____ ns t hc chip enable hold time 0.5 ____ 0.5 ____ ns t sb byte enable setup time 1.7 ____ 1.8 ____ ns t hb byte enable hold time 0.5 ____ 0.5 ____ ns t sw r/w setup time 1.7 ____ 1.8 ____ ns t hw r/w hold time 0.5 ____ 0.5 ____ ns t sd input data se tup time 1.7 ____ 1.8 ____ ns t hd input data ho ld time 0.5 ____ 0.5 ____ ns t sad ads setup time 1.7 ____ 1.8 ____ ns t had ads hold time 0.5 ____ 0.5 ____ ns t scn cnten setup time 1.7 ____ 1.8 ____ ns t hcn cnten hold time 0.5 ____ 0.5 ____ ns t srpt repeat setup time 1.7 ____ 1.8 ____ ns t hrpt repeat hold time 0.5 ____ 0.5 ____ ns t oe output enable to data valid ____ 4.0 ____ 4.2 ns t olz output enable to output low-z 1 ____ 1 ____ ns t ohz output enable to output high-z 1 3.6 1 4.2 ns t cd1 clock to data valid (flow-through) (1) ____ 12 ____ 15 ns t cd2 clock to data valid (pipelined) (1) ____ 3.6 ____ 4.2 ns t dc data outp ut ho ld afte r clock high 1 ____ 1 ____ ns t ckhz clock hig h to outp ut hig h-z 1 3 1 3 ns t cklz clock hig h to outp ut lo w-z 1 ____ 1 ____ ns port-to-port delay t co clock-to-clock offset 5 ____ 6 ____ ns 5623 tbl 11
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 12 an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 ub , lb (3) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 5623 drw 06 (1) (1) t sc t hc t sb t hb t sw t hw t sa t ha t dc t sc t hc t sb t hb (4) (1 latency) (5) (5) timing waveform of read cycle for pipelined operation ( ft /pipe 'x' = v ih ) (2) notes: 1. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 2. ads = v il , cnten and repeat = v ih . 3. the output is disabled (high-impedance state) by ce 0 = v ih , ce 1 = v il , ub , lb = v ih following the next rising edge of the clock. refer to truth table 1. 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. if ub , lb was high, then the appropriate byte of data out for qn + 2 would be disabled (high-impedance state). 6. "x" denotes left or right port. the diagram is with respect to that port. timing waveform of read cycle for flow-through output ( ft /pipe "x" = v il ) (2,6) an an + 1 an + 2 an + 3 t cyc1 t ch1 t cl1 r/ w address data out ce 0 clk oe t sc t hc t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 5623 drw 07 (5) (1) ce 1 ub , lb (3) t sb t hb t sw t hw t sa t ha t dc t dc (4) t sc t hc t sb t hb
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 13 t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz t sc t hc t ckhz t cklz t cd2 a 6 a 6 t dc t sc t hc t sc t hc 5623 drw 08 timing waveform of a multi-device pipelined read (1,2) notes: 1. b1 represents device #1; b2 represents device #2. each device consists of one idt70v3319/99 for this waveform, and are setup for depth expansion in this example. address (b1) = address (b2) in this situation. 2. ub , lb , oe , and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w , cnten , and repeat = v ih . timing waveform of a multi-device flow-through read (1,2) t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 5623 drw 09 d 0 d 3 t cd1 t cklz t ckhz (1) (1) d 1 data out(b1) t ch1 t cl1 t cyc1 (1) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) d 2 d 4 t cd1 t cd1 t ckhz t dc t cd1 t cklz t sc t hc (1) t ckhz (1) t cklz (1) t cd1 a 6 a 6 t dc t sc t hc t sc t hc d 5 t cd1 t cklz (1) t ckhz (1)
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 14 clk "a" r/ w "a" address "a" data in"a" clk "b" r/ w "b" address "b" data out"b" t sw t hw t sa t ha t sd t hd t sw t hw t sa t ha t co (3) t cd2 no match valid no match match match valid 5623 drw 10 t dc timing waveform of left port write to pipelined right port read (1,2,4) notes: 1. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 2. oe = v il for port "b", which is being read from. oe = v ih for port "a", which is being written to. 3. if t co < minimum specified, then data from port "b" read is not valid until following port "b" clock cycle (ie, time from write to val id read on opposite port will be t co + 2 t cyc2 + t cd2 ). if t co > minimum, then data from port "b" read is available on first port "b" clock cycle (ie, time from write to valid read on oppos ite port will be t co + t cyc2 + t cd2 ). 4. all timing is the same for left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a" timing waveform with port-to-port flow-through read (1,2,4) data in "a" clk "b" r/ w "b" address "a" r/ w "a" clk "a" address "b" no match match no match match valid t cd1 t dc data out "b" 5623 drw 11 valid valid t sw t hw t sa t ha t sd t hd t hw t cd1 t co t dc t sa t sw t ha (3) notes: 1. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 2. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 3. if t co < minimum specified, then data from port "b" read is not valid until following port "b" clock cycle (i.e., time from write to v alid read on opposite port will be t co + t cyc + t cd1 ). if t co > minimum, then data from port "b" read is available on first port "b" clock cycle (i.e., time from write to valid read on oppo site port will be t co + t cd1 ). 4. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a".
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 15 r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5623 drw 12 qn qn + 3 data out ce 1 ub , lb t cd2 t ckhz t cklz t cd2 t sc t hc t sb t hb t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (3) (1) t sw t hw write (4) timing waveform of pipelined read-to-write-to-read ( oe = v il ) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . "nop" is "no operation". 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 5623 drw 13 data out qn qn + 4 ce 1 ub , lb oe t ch2 t cl2 t cyc2 t cklz t cd2 t ohz t cd2 t sd t hd read write read t sc t hc t sb t hb t sw t hw t sa t ha (3) (1) t sw t hw (4) timing waveform of pipelined read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. this timing does not meet requirements for fastest speed grade. this waveform indicates how logically it could be done if tim ing so allows.
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 16 timing waveform of flow-through read-to-write-to-read ( oe = v il ) (2) timing waveform of flow-through read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 6523 drw 14 qn data out ce 1 ub , lb t cd1 qn + 1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read nop read t cklz (3) (1) t sw t hw write (5) r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 (3) data in dn + 2 ce 0 clk 5623 drw 15 qn data out ce 1 ub , lb t cd1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read write read t cklz (1) dn + 3 t ohz t sw t hw oe t oe
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 17 address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 5623 drw 16 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 timing waveform of pipelined read with address counter advance (1) notes: 1. ce 0 , oe , ub , lb = v il ; ce 1 , r/ w , and repeat = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. timing waveform of flow-through read with address counter advance (1) address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 5623 drw 17 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 18 address an d 0 t ch2 t cl2 t cyc2 q last q last+1 last ads load clk data in r/ w repeat 5623 drw 19 internal (3) address ads cnten t srpt t hrpt t sd t hd t sw t hw execute repeat write last ads address read last ads address read last ads address + 1 read address n qn an + 1 an + 2 read address n+1 data out t sa t ha last ads +1 an an + 1 (4) (5) (6) ax t sad t had t scn t hcn timing waveform of write with address counter advance (flow-through or pipelined inputs) (1) timing waveform of counter repeat (2) notes: 1. ce 0 , ub , lb , and r/ w = v il ; ce 1 and repeat = v ih . 2. ce 0 , ub , lb = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during repeat operation. a read or write cycle may be coincidental with the counter repeat cycle: address loaded by last valid ads load will be accessed. extra cycles are shown here simply for clarification. for more information on repeat function refer to truth table ii. 7. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. t he ?an +1?address is written to during this cycle. address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten t ch2 t cl2 t cyc2 5623 drw 18 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd t scn t hcn
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 19 functional description the idt70v3319/99 provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the low to high transition of the clock signal. an asynchronous output enable is provided to ease asyn- chronous bus interfacing. counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. a high on ce 0 or a low on ce 1 for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt70v3319/99s for depth expansion configurations. two cycles are required with ce 0 low and ce 1 high to re-activate the outputs. 5623 drw 20 idt70v3319/99 ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 a 18 /a 17 (1) ce 1 ce 0 v dd v dd idt70v3319/99 idt70v3319/99 idt70v3319/99 control inputs control inputs control inputs control inputs ub , lb , r/ w , oe , clk, ads , repeat , cnten depth and width expansion the idt70v3319/99 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70v3319/99 can also be used in applications requiring expanded width, as indicated in figure 4. through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 36-bits or wider. figure 4. depth and width expansion with idt70v3319/99 note: 1. a 17 is for idt70v3319, a 16 is for idt70v3399.
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 20 jtag ac electrical characteristics (1,2,3,4) 70v3319/99 symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1) ns t jf jtag clock fall time ____ 3 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc j tag data outp ut ho ld 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5623 tbl 12 notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. jtag timing specifications tck device inputs (1) / tdi/tms device outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch 5623 drw 21 , figure 5. standard jtag timing notes: 1. device inputs = all device inputs except tdi, tms, and trst. 2. device outputs = all device outputs except tdo.
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 21 identification register definitions instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x0314 (1) defines idt part number idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register 5623 tbl 13 scan register sizes register name bit size instruction (ir) 4 bypass (byr) 1 id entificatio n (idr) 32 boundary scan (bsr) note (3) 5623 tbl 14 system interface parameters instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. bypass 1111 places the bypass register (byr) between tdi and tdo. idcode 0010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 0011 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. sample/preload 0001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2 ) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the b oundary scan cells via the tdi. reserved all other codes several combinations are reserved. do not use codes other than those identified above. 5623 tbl 15 notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst . 3. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by conta cting your local idt sales representative. note: 1. device id for idt70v3399 is 0x0315.
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 22 ordering information a power 999 speed a package a process/ temperature range blank i commercial (0c to +70c) industrial (-40c to +85c) bf prf bc 208-pin fpbga (bf-208) 128-pin tqfp (pk-128) 256-pin bga (bc-256) 166 133 xxxxx device type idt speed in megahertz 5623 drw 22 s standard power 70v3319 70v3399 4mbit (256k x 18-bit) synchronous dual-port ram 2mbit (128k x 18-bit) synchronous dual-port ram commercial only commercial & industrial idt dual-port part number dual-port i/o specitications clock specifications idt pll clock device voltage i/o input capacitance input duty cycle requirement maximum frequency jitter to l e ra n c e 70v3319/99 3.3/2.5 lvttl 8pf 40% 166 75ps idt5v2528 5623 tbl 16a idt clock solution for idt70v3319/99 dual-port
6.42 idt70v3319/99s high-speed 3.3v 256/128k x 18 dual-port synchronous static ram industrial and commercial temperature ranges 23 datasheet document history: 06/02/00: initial public offering 07/12/00: page 1 added mux to functional block diagram 06/20/01: page 1 added jtag information for tqfp package page 4 corrected tqfp package size 07/30/01: page 1 added pl/ ft option page 20 changed maximum value for jtag ac electrical characteristics for t jcd from 20ns to 25ns page 9 added industrial temperature dc parameters 11/20/01: page 2, 3 & 4 added date revision for pin configurations page 11 changed t oe value in ac electrical characteristics, please refer to errata #smen-01-05 page 1 & 22 replaced tm logo with ? logo page 10 changed ac test conditions input rise/fall times 08/06/02: consolidated multiple devices into one datasheet page 1 & 5 added dcd capability for pipelined outputs page 7 clarified t bias and added t jn page 9 changed dc electrical parameters page 11 removed clock rise & fall time from ac electrical characteristics table removed preliminary status 05/19/03: page 11 added byte enable setuptime & byte enable hold time to ac elecctrical characteristics table page 22 added idt clock solution table the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-5166 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com

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